%FILENAME%
verilator-4.024-1-x86_64.pkg.tar.zst

%NAME%
verilator

%BASE%
verilator

%VERSION%
4.024-1

%DESC%
The fastest free Verilog HDL simulator

%CSIZE%
3835005

%ISIZE%
17204830

%SHA256SUM%
71678f3492fd67dd94e73d099ed6a8f09895b292c84aeb6761875280f59c592c

%PGPSIG%
iQIzBAABCAAdFiEEtZcfLFwQqaCMYAMPeGxj8zDXy5IFAl4odCAACgkQeGxj8zDXy5J3Pw//VwNEvAcpOq3l2gKMgMYrteTjqoD8uub5+oQbZB+e/+/Yhyvq5nRBkXG7vIzHdD3Z5hN0mx9vyWVceC19dEnoZw9o2uCtKp9mFszmFzlv+KgIE2ELLjFah14VMiTtyZOmJ8bhA+DmATU6hPUiJm3TD2b+JaFzNtYlhXK83WXLfmufIJs2MIeT6+aOIOy0tvONMbyRX5Z2wZxirZTBzW5xVG3UHDE2p+KAXchlsN9dt1A3eZeyhxUOBz1tL93YIkEszV8scbI2c6S8e8Lz9OvinviIUnNWPQ5jBeJyyCBwHL306F2Wsr+5867rIwvAU6gomXu8QvHe3Hi1pV3dcdlB1Slw3Uy1jWHHDcbssrJ5RU9qD3UJopDj+bL7xPaSd9xpQ8Gut5C2V5pT4V7q44XqTX6q9jKUe9AsjOEKoXH5w3lZui14s4bFeav1oSBM/vBVv5rVGAoc5MpfugnFAjp43NtYHr0+/XFSv0YiQUMbRY5rniQCkyaitjzvch1DyWcOQWxLX42bFr4qrAdPr7+ffoX/Jwbzzx7qalIoMO8fw75NoDMDYAxmwPXNZvYexxOjyoTo37ZoxpDXWvC9LWY3RrpISWFlXxGR1r/7rcW9b/FH6OYABJ0jVP0vcj8DH6rnWYs9YR/EruZUsB2o4qYapLirBT3v/KRVCl3VXa6nQm0=

%URL%
https://www.veripool.org/projects/verilator/wiki/Intro

%LICENSE%
LGPL

%ARCH%
x86_64

%BUILDDATE%
1579709300

%PACKAGER%
Felix Yan <felixonmars@archlinux.org>

%DEPENDS%
gcc-libs

%MAKEDEPENDS%
gcc

